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rev. 1.10 1 february 03, 2015 rev. 1.00 pb february 03, 2015 ht1380a/ht1381a serial timekeeper chip features ? operating voltage: 2.0v~5.5v ? maximum input serial clock: 500khz at v dd =2v, 2mhz at v dd =5v ? operating current: C less than 0.5a at 2v C less than 0.7a at 3v C less than 1.0a at 5v ? ttl compatible C v ih : 2.0v~v dd +0.3v at v dd =5v C v il : 0.3v~+0.8v at v dd =5v ? two data transmission modes: single-byte, or burst mode ? serial i/o transmission ? all registers store bcd format ? ht1380a: 8-pin dip package ht1381a: 8-pin sop package applications ? microcomputer serial clock ? clock and calendar general description the ht1380a/ht1381a is a serial timekeeper ic which provides seconds, minutes, hours, day, date, month and year information. the number of days in each month and leap years are automatically adjusted. the ht1380a/ht1381a is designed for low power consumption and can operate in two modes: one is the 12-hour mode with an am/pm indicator, the other is the 24-hour mode. the ht1380a/ht1381a has several registers to store the corresponding information with 8-bit data format. a 32768hz crystal is required to provide the correct timing. in order to minimize the pin number, the ht1380a/ht1381a use a serial i/o transmission method to interface with a microprocessor. only three wires are required: (1) rest , (2) sclk and (3) i/o. data can be delivered 1 byte at a time or in a burst of up to 8 bytes. block diagram
? pin assignment

rev. 1.10 2 february 03, 2015 ht1380a/ht1381a pad assignment

chip size: 1136 900 (m) 2 * the ic substrate should be connected to vss in the pcb layout artwork. pad coordinates unit: m pad no. x y 1 -456.985 333.025 2 -456.985 264.025 3 -456.985 195.025 4 -455.590 109.935 5 -466.000 -154.955 6 -466.000 -249.955 7 -466.000 -344.955 8 465.966 -309.630 9 465.966 -214.630 10 465.966 -119.630 11 465.966 -24.630 pad description pin name i/o internal connection description vss ? cmos negative power supply, ground x1 i cmos 32768hz crystal input pad x2 o cmos oscillator output pad rest i cmos reset pin with serial transmission i/o i/o cmos data input/output pin with serial transmission sclk i cmos serial clock pulse pin with serial transmission vdd ? cmos positive power supply
rev. 1.10 3 february 03, 2015 ht1380a/ht1381a absolute maximum ratings supply voltage ....................................... -0.3v ~ 5.5v input voltage ............................. v ss -0.3v ~ v dd +0.3v storage temperature ............................ -50 ? c ~ 125 ? c operating temperature ........................... -40 ? c ~ 85 ? c note: these are stress ratings only. stresses exceeding the range specifed under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specifcation is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics 7d symbol parameter test conditions min. typ. max. unit v dd conditions i stb standby current 2v 100 na 3v 100 5v 100 i dd operating current 2v no load 0.30 0.50 3v 0.50 0.70 5v 0.85 1.00 i oh source current 2v v oh =1.8v -0.20 -0.40 p 3v v oh =2.7v -0.35 -0.70 5v v oh =4.5v -0.50 -1.00 i ol sink current 2v v ol =0.2v 0.70 1.50 p 3v v ol =0.3v 1.20 2.50 5v v ol =0.5v 2.00 4.00 v ih "h" input voltage 3v 2.00 v 5v 2.00 v il "l" input voltage 3v 0.60 v 5v 0.80 note: i stb is specifed with sclk, i/o, rest open. the clock halt bit must be set to logic 1 (oscillator disabled).
rev. 1.10 4 february 03, 2015 ht1380a/ht1381a a.c. characteristics ta=25?c symbol parameter test conditions min. typ. max. unit v dd conditions t dc data to clock setup 2v 200 ns 3v 100 5v 50 t cdh clock to data hold 2v 280 ns 3v 140 5v 70 t cdd clock to data delay 2v 800 ns 3v 400 5v 200 t cl clock low time 2v 1000 ns 3v 500 5v 250 t ch clock high time 2v 1000 ns 3v 500 5v 250 f sclk clock frequency 2v 0.5 mhz 3v 1.0 5v 2.0 t r /t f clock rise and fall time 2v 2000 ns 3v 1000 5v 500 t cc reset to clock setup 2v 4 s 3v 2 5v 1 t cch clock to reset hold 2v 240 ns 3v 120 5v 60 t cwh reset inactive time 2v 4 s 3v 2 5v 1 t cdz reset to i/o high impedance 2v 280 ns 3v 140 5v 70
rev. 1.10 5 february 03, 2015 ht1380a/ht1381a functional description the ht1380a/ht1381a mainly contains the following internal elements: a data shift register array to store the clock/calendar data, command control logic, oscillator circuit and read timer clock. the clock is contained in eight read/write registers as shown below. data contained in the clock register is in binary coded decimal format. two modes are available for transferring the data between the microprocessor and the ht1380a/ ht1381a. one is in single-byte mode and the other is in multiple-byte mode. the ht1380a/ht1381a also contains two additional bits, the clock halt bit (ch) and the write protect bit (wp). these bits control the operation of the oscillator and so data can be written to the register array. these two bits should frst be specifed in order to read from and write to the register array properly. command byte for each data transfer, a command byte is initiated to specify which register is accessed. this is to determine whether a read, write, or test cycle is operated and whether a single byte or burst mode transfer is to occur. refer to the table shown below and follow the steps to write the data to the chip. first give a command byte of ht1380a/ht1381a, and then write a data in the register. this table illustrates the correlation between command byte and their bits: function description command byte c7 c6 c5 c4 c3 c2 c1 c0 select read or write cycle r/w specify the register to be accessed a2 a1 a0 clock halt flag c for ic test only 1 0 0 1 x x x 1 select single byte or burst mode 1 0 1 1 1 1 1 x note: x stands for dont care the following table shows the register address and its data format: register name range data register defnition address a2~a0 bit r/w command byte d7 d6 d5 d4 d3 d2 d1 d0 seconds 00~59 ch 10 sec sec 000 w r 10000000 10000001 minutes 00~59 0 10 min min 001 w r 10000010 10000011 hours 01~12 00~23 12\ 24 0 0 ap 10 hr hr hour 010 w r 10000100 10000101 date 01~31 0 0 10 date date 011 w r 10000110 10000111 month 01~12 0 0 0 10m month 100 w r 10001000 10001001 day 01~07 0 0 0 0 day 101 w r 10001010 10001011 year 00~99 10 year year 110 w r 10001100 10001101 write protect 00~80 wp always zero 111 w r 10001110 10001111 ch: clock halt bit ch=0 oscillator enabled ch=1 oscillator disabled wp: write protect bit wp=0 register data can be written in wp=1 register data can not be written in bit 7 of reg2: 12/24 mode fag bit 7=1, 12-hour mode bit 7=0, 24-hour mode bit 5 of reg2: am/pm mode defned ap=1 pm mode ap=0 am mode
rev. 1.10 6 february 03, 2015 ht1380a/ht1381a r/w signal the lsb of the command byte determines whether the data in the register be read or be written to. when it is set as 0 means that a write cycle is to take place otherwise this chip will be set into the read mode. a0~a2 a0 to a2 of the command byte is used to specify which registers are to be accessed. there are eight registers used to control the month data, etc., and each of these registers have to be set as a write cycle in the initial time. burst mode when the command byte is 10111110 (or 10111111), the ht1380a/ht1381a is confgured in burst mode. in this mode the eight clock/calendar registers can be written (or read) in series, starting with bit 0 of register address 0 (see the timing on the next page). test mode when the command byte is set as 1001xxx1, ht1380a/ht1381a is confgured in test mode. the test mode is used by holtek only for testing purposes. if used generally, unpredictable conditions may occur. write protect register this register is used to prevent a write operation to any other register. data can be written into the designated register only if the write protect signal (wp) is set to logic 0. the write protect register should be set first before restarting the system or before writing the new data to the system, and it should set as logic 1 in the read cycle. the write protect bit cannot be written to in the burst mode. clock halt bit d7 of the seconds register is defined as the clock halt flag (ch). when this bit is set to logic 1, the clock oscillator is stopped and the chip goes into a low-power standby mode. when this bit is written to logic 0, the clock will start. 12-hour/24-hour mode the d7 of the hour register is defned as the 12-hour or 24-hour mode select bit. when this bit is in high level, the 12-hour mode is selected otherwise its the 24-hour mode. am-pm mode these are two functions for the d5 of the hour register determined by the value d7 of the same register. one is used in am/pm selection on the 12-hour mode. when d5 is logic 1, it is pm, otherwise its am. the other is used to set the second 10-hour bit (20~23 hours) on the 24-hour mode. reset and serial clock control the rest pin is used to allow access data to the shift register like a toggle switch. when the rest pin is taken high, the built-in control logic is turned on and the address/command sequence can access the corresponding shift register. the rest pin is also used to terminate either single-byte or burst mode data format. the input signal of sclk is a sequence of a falling edge followed by a rising edge and it is used to synchronize the register data whether read or write. for data input, the data must be read after the rising edge of sclk. the data on the i/o pin becomes output mode after the falling edge of the sclk. all data transfer terminates if the rest pin is low and the i/o pin goes to a high impedance state. the data transfer is illustrated on the next page. data input and data out i n writing a data byte with ht1380a/ht1381a, the read/write should frst set as r/w=0 in the command byte and follow with the corresponding data register on the rising edge of the next eight sclk cycles. additional sclk cycles are ignored. data inputs are entered starting with bit 0. in reading a data on the register of ht1380a/ ht1381a, r/w=1 should first be entered as input. the data bit outputs on the falling edge of the next eight sclk cycles. note that the frst data bit to be transmitted on the frst falling edge after the last bit of the read command byte is written. additional sclk cycles re-transmits the data bytes as long as rest remains at high level. data outputs are read starting with bit 0. crystal selection a 32768hz crystal can be directly connected to the ht1380a/ht1381a on pins 2 and 3 which are the crystal x1 and x2 pins. in order to ensure that the desired frequency is achieved, it is recommended to use a crystal with a capacitance of 9.0pf. it is not recommended that additional load capacitors are connected to the x1 and x2 pins. refer to the following page for the crystal specifcations.
rev. 1.10 7 february 03, 2015 ht1380a/ht1381a the following diagram shows the single and burst mode transfer: single byte transfer

burst mode transfer
crystal specifcations symbol parameter min. typ. max. unit f o 1rpldouhtxhf\ 32.768 khz esr series resistance 50 n c l load capacitance 9.0 pf note: 1. it is strongly recommended to use a crystal with a load capacitance of 9.0pf. never use a crystal with a load capacitance of 12.5pf. 2. the oscillator selection can be optimized using a high quality resonator with a small esr value. refer to the crystal manufacturer for more details: www.microcrystal.com. operating flowchart to initiate any transfer of data, rest is taken high and an 8-bit command byte is frst loaded into the control logic to provide the register address and command information. following the command word, the clock/ calendar data is serially transferred to or from the corresponding register. the rest pin must be taken low again after the transfer operation is completed. all data enter on the rising edge of sclk and outputs on the falling edge of sclk. in total, 16 clock pulses are needed for a single byte mode and 72 for burst mode. both input and output data starts with bit 0. in using the ht1380a/ht1381a, set frst the wp and ch to 0 and wait for about 3 seconds, the oscillator will generate the clocks for internal use. then, choose either single mode or burst mode to input the data. the read or write operating fowcharts are shown on the next page.
rev. 1.10 8 february 03, 2015 ht1380a/ht1381a

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? note: * in reading data byte from ht1380a/ht1381a register, the frst data bit to be transmitted at the frst falling edge after the last bit of the command byte is written.
rev. 1.10 9 february 03, 2015 ht1380a/ht1381a timing diagrams read data transfer

write data transfer
application circuit

note: * in order to obtain the correct frequency, it is recommended to use a crystal with a load capacitance of 9.0pf. it is not recommended to connect load capacitors to the x1 and x2 pins. if the power line is noisy, it is recommended to add r1 and c1 for fltering out noise.
rev. 1.10 10 february 03, 2015 ht1380a/ht1381a package information note that the packag e information provided here is for consultation purposes on ly. as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package/carton information . additional supplementary information with regard to p ackaging is listed below. click o n the relevant section to be transferred to the relevant website page. ? further package information (include outline dimensions, product tape and reel specifcations) ? packing meterials information ? carton information
rev. 1.10 11 february 03, 2015 ht1380a/ht1381a 8-pin dip (300mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.355 0.365 0.400 b 0.240 0.250 0.280 c 0.115 0.130 0.195 d 0.115 0.130 0.150 e 0.014 0.018 0.022 f 0.045 0.060 0.070 g 0.100 bsc h 0.300 0.310 0.325 i 0.430 symbol dimensions in mm min. nom. max. a 9.02 9.27 10.16 b 6.10 6.35 7.11 c 2.92 3.30 4.95 d 2.92 3.30 3.81 e 0.36 0.46 0.56 f 1.14 1.52 1.78 g 2.54 bsc h 7.26 7.87 8.26 i 10.92
rev. 1.10 12 february 03, 2015 ht1380a/ht1381a 8-pin sop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.236 bsc b 0.154 bsc c 0.012 0.020 c 0.193 bsc d 0.069 e 0.050 bsc f 0.004 0.010 g 0.016 0.050 h 0.004 0.010 0 8 symbol dimensions in mm min. nom. max. a f 6.00 bsc b 3.90 bsc c 0.31 0.51 c 4.90 bsc d 1.75 e 1.27 bsc f 0.10 0.25 g 0.40 1.27 h 0.10 0.25 0 8
rev. 1.10 13 february 03, 2015 ht1380a/ht1381a copyright ? 2015 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifcations described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notifcation. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

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